The present invention relates to rate converting apparatus for converting clock rates of digital signals.
In order for two digital circuits operating at different clock rates to communicate with one another, a rate convertor must convert the clock rates of digital signals communicated between these two circuits. In the case of an image pickup device transmitting digital video data to the digital signal processing circuit of a digital video tape recorder utilizing the D-1 format, the digital video data must be down-converted from a clock rate of, for example, 18 MHz to a clock rate of 13.5 MHz. Similarly, it may be necessary to up-convert the digital video data having the clock rate of 13.5 MHz to the clock rate of 18 MHz when digital video signals reproduced by the digital video tape recorder are transmitted to an output device having a clock rate of 18 MHz.
A known down conversion apparatus for converting the clock rate of an input digital signal from a relatively high input clock rate to a relatively lower output clock rate, first obtains a digital signal having a clock rate equal to the least common multiple of the input clock rate and the output clock rate by means of up-converting the original input digital signal. That is, if a digital signal having a clock rate of 18 MHz is supplied to the apparatus and it is desired to down-convert the clock rate to 13.5 MHz, the input digital signal is up-converted to a clock rate of 54 MHz, the least common multiple of 13.5 MHz and 18 MHz, before it is down-converted to the clock rate of 13.5 MHz.
The aforementioned known down-rate conversion process will be described with reference to the time domain diagrams of FIGS. 1(A) to 1(E) and the frequency domain diagrams of FIGS. 2(A) to 2(E). Using the above example of down-converting a digital signal from the clock rate of 18 MHz to the clock rate of 13.5 MHz, FIG. 1(A) illustrates an input signal {X.sub.n } having a clock rate of 18 MHz, wherein the input data has a spectrum as shown in FIG. 2(A). During down-conversion, "0" data points are inserted at empty locations in the signal which correspond to sample points of a signal having the clock rate of 54 MHz, which is the least common multiple of 13.5 MHz and 18 MHz, resulting in the signal shown in FIG. 1(B) halving a spectrum shown in FIG. 2(B) .
The 54 MHz data is filtered by a filter having a characteristic as shown in FIG. 1(C) and in FIG. 2(C). Because the clock rate of the output signal is 13.5 MHz, if there are frequency components above 6.75 MHz, other than the 54 MHz component, the output signal suffers distortion due to aliasing. Consequently, these frequency components are suppressed by a low pass filter. The filtered signal, designated Y.sub.n hereinbelow, as shown in FIG. 1(D) has a clock rate of 54 MHz and a frequency spectrum as illustrated in FIG. 2(D).
The filter supplies the time domain data {Y.sub.n }, by utilizing the filter transfer function: ##EQU1##
This transfer function employs twelve taps (j=0 to j=11), where z.sup.-j indicates the amount of delay of the input signal X such that X.sub.n+1 =z.sup.-n *X.sub.1. The data Y.sub.n for each of fourteen successive clock cycles (n=1 to 14) are calculated by the following equations: EQU Y.sub.1 =k.sub.2 *X.sub.4 =k.sub.5 *X.sub.3 =k.sub.8 *X.sub.2 =k.sub.11 *X.sub.1 EQU Y.sub.2 =k.sub.0 *X.sub.5 =k.sub.3 *X.sub.4 =k.sub.6 *X.sub.3 =k.sub.9 *X.sub.2 EQU Y.sub.3 =k.sub.1 *X.sub.5 =k.sub.4 *X.sub.4 =k.sub.7 *X.sub.3 =k.sub.10 *X.sub.2 EQU Y.sub.4 =k.sub.2 *X.sub.5 =k.sub.5 *X.sub.4 =k.sub.8 *X.sub.3 =k.sub.11 *X.sub.2 EQU Y.sub.5 =k.sub.0 *X.sub.6 =k.sub.3 *X.sub.5 =k.sub.6 *X.sub.4 =k.sub.9 *X.sub.3 EQU Y.sub.6 =k.sub.1 *X.sub.6 =k.sub.4 *X.sub.5 =k.sub.7 *X.sub.4 =k.sub.10 *X.sub.3 EQU Y.sub.7 =k.sub.2 *X.sub.6 =k.sub.5 *X.sub.5 =k.sub.8 *X.sub.4 =k.sub.11 *X.sub.3 EQU Y.sub.8 =k.sub.0 *X.sub.7 =k.sub.3 *X.sub.6 =k.sub.6 *X.sub.5 =k.sub.9 *X.sub.4 EQU Y.sub.9 =k.sub.1 *X.sub.7 =k.sub.4 *X.sub.6 =k.sub.7 *X.sub.5 =k.sub.10 *X.sub.4 EQU Y.sub.10 =k.sub.2 *X.sub.7 =k.sub.5 *X.sub.6 =k.sub.8 *X.sub.5 =k.sub.11 *X.sub.4 EQU Y.sub.11 =k.sub.0 *X.sub.8 =k.sub.3 *X.sub.7 =k.sub.6 *X.sub.6 =k.sub.9 *X.sub.5 EQU Y.sub.12 =k.sub.1 *X.sub.8 =k.sub.4 *X.sub.7 =k.sub.7 *X.sub.6 =k.sub.10 *X.sub.5 EQU Y.sub.13 =k.sub.2 *X.sub.8 =k.sub.5 *X.sub.7 =k.sub.8 *X.sub.6 =k.sub.11 *X.sub.5 EQU Y.sub.14 =k.sub.0 *X.sub.9 =k.sub.3 *X.sub.8 =k.sub.6 *X.sub.7 =k.sub.9 *X.sub.6
The above calculations are repeated every fourteen clock cycles to provide successive values of Y.sub.n. The resulting 54 MHz digital signal is down-converted to a clock rate of 13.5 MHz by merely selecting data at a clock rate of 13.5 MHz as shown in FIG. 1(E), the resulting data having a frequency domain characteristic as shown in FIG. 2(E). Since the down-converted clock signal contains all of the frequency components of the input signal {X.sub.n }, distortion is avoided.
A known up-rate conversion apparatus will be described with reference to the time domain diagrams of FIGS. 3(A) to 3(E) and the frequency domain diagrams of FIGS. 4(A) to 4(E). FIG. 3(A) illustrates an input signal {X.sub.n } having a clock rate of 13.5 MHz, the input data having a spectrum shown in FIG. 4(A). During up-conversion, "0" data points are inserted at empty locations in the signal which correspond to sample points of a signal having a clock rate of 54 MHz, as the least common multiple of 18 MHz and 13.5 MHz, resulting in the signal shown in FIG. 3(B) having a spectrum shown in FIG. 4(B).
The data whose clock rate is 54 MHz is filtered by a filter having the characteristics shown in FIG. 3(C) and in FIG. 4(C). Because the clock rate of the output signal is 18 MHz, frequency components above 9 MHz cause distortion due to aliasing, and thus, these frequency components are suppressed by a low pass filter. The filtered signal Y.sub.n shown in FIG. 3(D), has a clock rate of 54 MHz and a frequency spectrum as illustrated in FIG. 4(D).
The filter supplies the time domain data {Y.sub.n } by utilizing the filter transfer function: ##EQU2##
This transfer function employs twelve taps (j=0 to j=11), where z.sup.-j indicates the amount of delay of the input signal X, such that X.sub.n+1 =z.sup.-n *X.sub.1, Y.sub.1 to Y.sub.14. The data Y.sub.n for each of fourteen successive clock cycles are calculated by the following equations: EQU Y.sub.1 =k.sub.3 *X.sub.3 =k.sub.7 *X.sub.2 =k.sub.11 *X.sub.1 EQU Y.sub.2 =k.sub.0 *X.sub.4 =k.sub.4 *X.sub.3 =k.sub.8 *X.sub.2 EQU Y.sub.3 =k.sub.1 *X.sub.4 =k.sub.5 *X.sub.3 =k.sub.9 *X.sub.2 EQU Y.sub.4 =k.sub.2 *X.sub.4 =k.sub.6 *X.sub.3 =k.sub.10 *X.sub.2 EQU Y.sub.5 =k.sub.3 *X.sub.4 =k.sub.7 *X.sub.3 =k.sub.11 *X.sub.2 EQU Y.sub.6 =k.sub.0 *X.sub.5 =k.sub.4 *X.sub.4 =k.sub.8 *X.sub.3 EQU Y.sub.7 =k.sub.1 *X.sub.5 =k.sub.5 *X.sub.4 =k.sub.9 *X.sub.3 EQU Y.sub.8 =k.sub.2 *X.sub.5 =k.sub.6 *X.sub.4 =k.sub.10 *X.sub.3 EQU Y.sub.9 =k.sub.3 *X.sub.5 =k.sub.7 *X.sub.4 =k.sub.11 *X.sub.3 EQU Y.sub.10 =k.sub.0 *X.sub.6 =k.sub.4 *X.sub.5 =k.sub.8 *X.sub.4 EQU Y.sub.11 =k.sub.1 *X.sub.6 =k.sub.5 *X.sub.5 =k.sub.9 *X.sub.4 EQU Y.sub.12 =k.sub.2 *X.sub.6 =k.sub.6 *X.sub.5 =k.sub.10 *X.sub.4 EQU Y.sub.13 =k.sub.3 *X.sub.6 =k.sub.7 *X.sub.5 =k.sub.11 *X.sub.4 EQU Y.sub.14 =k.sub.0 *X.sub.7 =k.sub.4 *X.sub.6 =k.sub.8 *X.sub.5
The above calculations are repeated every fourteen clock cycles to provide successive values of Y.sub.n. The resulting 54 MHz digital signal is down-converted to a clock rate of 18 MHz by selecting data at a clock rate of 18 MHz as shown in FIGS. 3(E) and 4(E). Since the down-converted clock signal contains all of the frequency components of the input signal {X.sub.n }, distortion is avoided.
Where it is desired to employ an 18 MHz clock rate digital camcorder with a D-1 digital VTR (having a 13.5 MHz clock rate), both a down rate converter and an up rate converter are required. Consequently, these prior art arrangements are relatively complex.